ML506_Gerber_Plots

01 OF 25 L1_TOP

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

Oct 04 2006

02 OF 25 L2_PWR

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

Oct 04 2006

03 OF 25 L3_GND

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

Oct 04 2006

04 OF 25 L4_SIG

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

Oct 04 2006

05 OF 25 L5_SIG

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

Oct 04 2006

06 OF 25 L6_GND

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

Oct 04 2006

07 OF 25 L7_SIG

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

Oct 04 2006

08 OF 25 L8_SIG

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

Oct 04 2006

09 OF 25 L9_GND

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

Oct 04 2006

10 OF 25 L10_SIG

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

Oct 04 2006

11 OF 25 L11_PWR

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

Oct 04 2006

Oct 04 2006

12 OF 25 L12_GND

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

Oct 04 2006

13 OF 25 L13_GND

Designed by Xilinx

LAYER:

ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415
ARTMASTER # 0531630

CLK GEN JTAG

1

DVI

RTSEL

1

TX DISAB

USB

1

1

SPDIF

HOST

USB

Systems Engineering Group

ML505-ML509

VIRTEX-5

VIDEO IN

10/100/1000 ETHERNET

SFP

1

ENET MODE SEL

1

PC4 JTAG

LNK

SFP

USB PERIPH

REV A

SEL

CLK

SATA

1

DIFF CLK IN

1

19 OF 25 SILK-SCREEN TOP

SYSACE

PROG

USB ABORT BOOT

FAILSAFE

SACE

1

CFG0

CFG1

CFG2

1

PROG

CLK JTAG

1

PS/2

MOUSE

PCIE FINGER 1X

P

RST

CPU

RST

1

N

TRACE/DEBUG

MOD0

MOD1

MOD2

1

KEYB

1

LEDS

ENET

SATA HOST 2

SATA HOST 1

3V3 REG

MOUSE

EN

BCK

FALL

SACE

RX

TX

DUP

BYP

CHAR LCD

1FAN

TXP

TXN

1

10

1

MGT

RXP

RXN

1V0 REG

PS/2

KEYB

1000

100

ERR2

ERR1

FAN

BDM

1

GPI/O

0

1

2

1V8

COM1

1

3

1

COM2

1

4

USR OSC

SUPRCLK

SYSMON HDR

LINE OUT

COM1

GPI/O

5

6

7

1

1

SACE

STAT

ERR

AVDD SEL

DONE

INIT

CONTRAST

PLAT FASH 1

SEL

CLKOUT

LVDS

HEADPHONE

1

3V3

GND

TCK

TDO

1

TDI

TMS

INIT

BATT

1

1

LINE IN

SPI PROG

FRONT PANEL AUDIO

MICROPHONE

c

P

DIFF CLK OUT

VCCO_SEL

N

5V

2006 Xilinx, Incorporated

PIEZO

3V3

1

3V3

W

SOFTOUCH PRO

1V8 REG

1

2V5

S

N

USR CLOCK

GPIO DIP SW

C

ENCODER

GND

PINS

DIFF

64

2V5

OFF

E

SCL

SDA

64

GND

LED3

LED0

LED1

LED2

SWS

LEDE

SWE

LEDW

SWW

LEDS

SWN

LEDC

SWC

TDO

TDI

LEDN

TMS

TCK

VCC3V3

VCC5V

XGI

62