bpc-los_10 - Greyův_C, tristate IO, simulace, ošetření metastability
Níže je uveden pouze náhled materiálu. Kliknutím na tlačítko 'Stáhnout soubor' stáhnete kompletní formátovaný materiál ve formátu PDF.
out
std_logic_vector(WIDTH - 1
downto 0));
end g_cnt;
architecture Behavioral of g_cnt is
signal cnt_gray : std_logic_vector(WIDTH - 1 downto 0);
signal bin_code : std_logic_vector(WIDTH - 1 downto 0);
signal bin_code_n : std_logic_vector(WIDTH - 1 downto 0);
constant cnt_init_val: std_logic_vector(WIDTH - 1 downto 0) := ('1', '1', others =>'0');
beginbin_code(WIDTH - 1) <= cnt_gray(WIDTH - 1);
-- Gray to binary
bin_code(WIDTH - 2
downto 0) <= cnt_gray(WIDTH - 2 downto 0) xor
bin_code(WIDTH - 1
downto 1);
-- next state (increment binary counter by 1)
bin_code_n <= std_logic_vector(UNSIGNED(bin_code) + 1);
process(CLK, rst)
begin
if rst = '1' then
cnt_gray <= cnt_init_val;
elsif CLK'event and CLK = '1' then
if EN = '1' then
-- binary to Gray
cnt_gray(WIDTH - 1) <= bin_code_n(WIDTH - 1);
-- Copy MSB
cnt_gray(WIDTH - 2
downto 0) <= bin_code_n(WIDTH - 2 downto 0) xor
bin_code_n(WIDTH - 1
downto 1);
end if;
end if;
end process;
CNT_OUT <= cnt_gray;
end Behavioral;
Programovatelná hradlová pole typu FPGA a jazyk VHDL
Programovatelná hradlová pole typu FPGA a jazyk VHDL
Příklad:
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor_sig is
port ( A, B, C
: in STD_LOGIC;
X, Y
: out STD_LOGIC);
END xor_sig;
architecture SIG_ARCH of xor_sig is
SIGNAL D
: STD_LOGIC;
BEGIN
SIG: PROCESS (A,B,C)
BEGIN
D <= A; -- ignorováno !!
X <= C xor D;
D <= B; -- přepsáno !!
Y <= C xor D;
END PROCESS;
END SIG_ARCH;
Programovatelná hradlová pole typu FPGA a jazyk VHDL
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor_var is
port (
A, B, C
: in STD_LOGIC;
X, Y
: out STD_LOGIC);
END xor_var;
architecture VAR_ARCH of xor_var is
BEGIN
VAR: PROCESS (A,B,C)
variable D: STD_LOGIC;
BEGIN
D := A;
X <= C xor D;
D := B;
Y <= C xor D;
END PROCESS;
END VAR_ARCH;
Programovatelná hradlová pole typu FPGA a jazyk VHDL