bpc-los_09 - Posuv. registry, VHDL-implementace sekv. obvodů
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Obousm. posuvný registr - obecná VHDL impl.
ENTITY generic_bidir_shift_reg IS GENERIC(N: positive := 8);
PORT(
clk, sd, dir, arst: IN std_logic;
Q: OUT std_logic_vector(N-1 DOWNTO 0);
);
END generic_bidir_shift_reg;
generic_bidir_shift_reg
clk
sd
dir
arst
Q[N-1...0]
reg[N-1...0]
Obousm. posuvný registr - obecná VHDL impl.
ENTITY generic_bidir_shift_reg IS GENERIC(N: positive := 8);
PORT(
clk, sd, dir, arst: IN std_logic;
Q: OUT std_logic_vector(N-1 DOWNTO 0);
);
END generic_bidir_shift_reg;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
generic_bidir_shift_reg
clk
sd
dir
arst
Q[N-1...0]
reg[N-1...0]
ARCHITECTURE Behavioral OF generic_bidir_shift_reg IS SIGNAL reg: std_logic_vector(N-1 DOWNTO 0);
BEGIN PROCESS (arst, clk)
BEGIN IF(arst = '1') THEN
reg <= (OTHERS => '0'); -- Async reset
ELSIF(rising_edge(clk)) THEN
IF(dir = '1') THEN
reg <= reg(N-2 DOWNTO 0) & sd; -- Sync serial shift left
ELSE reg <= sd & reg(N-1 DOWNTO 1); -- Sync serial shift right
END IF;
END IF;
END PROCESS;
Q <= reg;
END Behavioral;
Obousm. posuvný registr - obecná VHDL impl.
ENTITY generic_bidir_shift_reg IS GENERIC(N: positive := 8);
PORT(
clk, sd, dir, arst: IN std_logic;
Q: OUT std_logic_vector(N-1 DOWNTO 0);
);
END generic_bidir_shift_reg;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
generic_bidir_shift_reg
clk
sd
dir
arst
Q[N-1...0]
reg[N-1...0]
ARCHITECTURE Behavioral OF generic_bidir_shift_reg IS SIGNAL reg: std_logic_vector(N-1 DOWNTO 0);
BEGIN PROCESS (arst, clk)
BEGIN IF(arst = '1') THEN
reg <= (OTHERS => '0'); -- Async reset
ELSIF(rising_edge(clk)) THEN
IF(dir = '1') THEN
reg <= reg(N-2 DOWNTO 0) & sd; -- Sync serial shift left
ELSE reg <= sd & reg(N-1 DOWNTO 1); -- Sync serial shift right
END IF;
END IF;
END PROCESS;
Q <= reg;
END Behavioral;
Obousm. posuvný registr - obecná VHDL impl.
ENTITY generic_bidir_shift_reg IS GENERIC(N: positive := 8);
PORT(
clk, sd, dir, arst: IN std_logic;
Q: OUT std_logic_vector(N-1 DOWNTO 0);
);
END generic_bidir_shift_reg;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
generic_bidir_shift_reg
clk
sd
dir
arst
Q[N-1...0]
reg[N-1...0]
ARCHITECTURE Behavioral OF generic_bidir_shift_reg IS SIGNAL reg: std_logic_vector(N-1 DOWNTO 0);
BEGIN PROCESS (arst, clk)
BEGIN IF(arst = '1') THEN
reg <= (OTHERS => '0'); -- Async reset
ELSIF(rising_edge(clk)) THEN
IF(dir = '1') THEN
reg <= reg(N-2 DOWNTO 0) & sd; -- Sync serial shift left
ELSE reg <= sd & reg(N-1 DOWNTO 1); -- Sync serial shift right
END IF;
END IF;
END PROCESS;
Q <= reg;
END Behavioral;
Obousm. posuvný registr - obecná VHDL impl.
ENTITY generic_bidir_shift_reg IS GENERIC(N: positive := 8);
PORT(
clk, sd, dir, arst: IN std_logic;
Q: OUT std_logic_vector(N-1 DOWNTO 0);
);
END generic_bidir_shift_reg;