bpc-los_09 - Posuv. registry, VHDL-implementace sekv. obvodů
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
generic_shift_reg
clk
sd
load
arst
D[N-1...0]
Q[N-1...0]
reg[N-1...0]
ARCHITECTURE Behavioral OF generic_shift_reg IS SIGNAL reg: std_logic_vector(N-1 DOWNTO 0);
BEGIN PROCESS (arst, clk)
BEGIN IF(arst = '1') THEN
reg <= (OTHERS => '0'); -- Async reset
ELSIF(rising_edge(clk)) THEN
IF(load = '1') THEN
reg <= D; -- Sync parallel load
ELSE reg <= reg(N-2 DOWNTO 0) & sd; -- Sync serial shift
END IF;
END IF;
END PROCESS;
Q <= reg;
END Behavioral;
Posuvný registr - obecná VHDL implementace
ENTITY generic_shift_reg IS GENERIC(N: positive := 8);
PORT(
clk, sd, load, arst: IN std_logic;
D: IN std_logic_vector(N-1 DOWNTO 0);
Q: OUT std_logic_vector(N-1 DOWNTO 0);
);
END generic_shift_reg;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
generic_shift_reg
clk
sd
load
arst
D[N-1...0]
Q[N-1...0]
reg[N-1...0]
ARCHITECTURE Behavioral OF generic_shift_reg IS SIGNAL reg: std_logic_vector(N-1 DOWNTO 0);
BEGIN PROCESS (arst, clk)
BEGIN IF(arst = '1') THEN
reg <= (OTHERS => '0'); -- Async reset
ELSIF(rising_edge(clk)) THEN
IF(load = '1') THEN
reg <= D; -- Sync parallel load
ELSE reg <= reg(N-2 DOWNTO 0) & sd; -- Sync serial shift
END IF;
END IF;
END PROCESS;
Q <= reg;
END Behavioral;
Posuvný registr - obecná VHDL implementace
ENTITY generic_shift_reg IS GENERIC(N: positive := 8);
PORT(
clk, sd, load, arst: IN std_logic;
D: IN std_logic_vector(N-1 DOWNTO 0);
Q: OUT std_logic_vector(N-1 DOWNTO 0);
);
END generic_shift_reg;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Posuvný registr, využití komponenty
generic_shift_reg
clk
sd
'0'
arst
"0000000"
Q[N-1...0]
reg[N-1...0]
shiftClk
shiftARst
shiftD
shiftQ
Shift_register
Q[N-1]
ENTITY Shift_register IS PORT(
shiftD, shiftClk, shiftARst: IN std_logic;
shiftQ: OUT std_logic;
);
END Shift_register;
Posuvný registr, využití komponenty
generic_shift_reg
clk
sd
'0'
arst
"0000000"
Q[N-1...0]
reg[N-1...0]
shiftClk
shiftARst
shiftD
shiftQ
Shift_register
Q[N-1]
Přímé vložení komponenty
ENTITY Shift_register IS PORT(
shiftD, shiftClk, shiftARst: IN std_logic;
shiftQ: OUT std_logic;
);
END Shift_register;
generic_shift_reg
clk
sd
'0'
arst
"0000000"
Q[7...0]
reg[7...0]
shiftClk
shiftARst
shiftD
shiftQ
Shift_register
data[7]
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Přímé vložení komponenty
ENTITY Shift_register IS PORT(
shiftD, shiftClk, shiftARst: IN std_logic;
shiftQ: OUT std_logic;
);
END Shift_register;